There has been disclosed a processing method of a computer employing a multithreaded processor (see Patent Document 1). An active thread state where a thread is activated is stored in at least one hardware register. A background thread state expressing an execution situation of at least one background thread is stored in the at least one hardware register. In the multithreaded processor, at least one active thread is executed. An active thread state of the above-described at least one active thread is replaced with a subsequent state generated by executing the above-described at least one active thread in the multithreaded processor. The replaced active thread state of the active thread is compared with a background thread state of at least one background thread. This determines whether the replacement of the active thread state of the at least one active thread with the subsequent state causes the multithreaded processor to switch execution to the at least one background thread.
[Patent Document 1] Japanese Translation of PCT Application No. 2001-521216
A single arithmetic unit can execute instructions of a plurality of threads. However, when an execution cycle number of an instruction of a single thread among a plurality of threads is long, the instruction of the single thread uses a single arithmetic unit exclusively. In this case, instructions of the other threads turn to a standby state for a long time and quality of service (QoS: Quality of Service) of the other threads decreases significantly.